texasinstruments

texasinstruments
Sample Questions
1.  For a CMOS inverter, the transition slope of Vout vs Vin 
DC characteristics can be increased (steeper transition) by: 

a.   Increasing W/L of PMOS transistor
b.   Increasing W/L of NMOS transistor
c.   Increasing W/L of both transistors by the same factor
d.   Decreasing W/L of both transistor by the same factor
2.   Minimum number of 2-input NAND gates that will be required to implement 
the function:  Y = AB + CD + EF is
a.    4
b.    5
c.    6
d.    7
3.    Consider a two-level memory hierarchy system M1 & 
M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 
2 nanoseconds and the miss penalty (the time to get the data from M2 in case 
of a miss) is 100 nanoseconds. The probability that a valid data is found in 
M1 is 0.97. The average memory access time is:
a.   4.94 nanoseconds
b.   3.06 nanoseconds
c.   5.00 nanoseconds
d.   5.06 nanoseconds
4.   Interrupt latency is the time elapsed between:
a.   Occurrence of an interrupt and its detection by the CPU
b.   Assertion of an interrupt and the start of the associated ISR
c.   Assertion of an interrupt and the completion of the associated ISR
d.   Start and completion of associated ISR
5.   Which of the following is true for the function (A.B + A’.C + B.C)
a.   This function can glitch and can be further reduced
b.   This function can neither glitch nor can be further reduced
c.   This function can glitch and cannot be further reduced
d.   This function cannot glitch but can be further reduced
6.   For the two flip-flop configuration below, what is the relationship of 
the output at B to the clock frequency?
a.   Output frequency is 1/4th the clock frequency, with 50% duty cycle
b.   Output frequency is 1/3rd the clock frequency, with 50% duty cycle
c.   Output frequency is 1/4th the clock frequency, with 25% duty cycle
d.   Output frequency is equal to the clock frequency
         
7.The voltage on Node B is:
e.  0
f.  10
g.  –10
   
8.A CPU supports 250 instructions. Each instruction op-code has these fields:
·  The instruction type (one among 250)
·  A conditional register specification
·  3 register operands
·  Addressing mode specification for both source operands
The CPU has 16 registers and supports 5 addressing modes. What is the instruction 
op-code length in bits?
h.  32
i.  24
j.  30
k.  36
7.  In the iterative network shown, the output Yn of any stage N is 1 if the 
total number of 1s at the inputs starting from the first stage to the Nth stage 
is odd. (Each identical box in the iterative network has two inputs and two
outputs). The optimal logic structure for the box consists of:
a.  One AND gate and one NOR gate
b.  One NOR gate and one NAND gate
c.  Two XNOR gates
d.  One XOR gate
8.  Consider a circuit with N logic nets. If each net can be stuck-at either 
values 0 and 1, in how many ways can the circuit be faulty such that only one 
net in it can be faulty, and such that up-to all nets in it can be faulty?
a.   2 and 2N
b.  N and 2^N
c.  2N and 3^N-1
d.  2N and 3N
 In the circuit shown, all the flip-flops are identical. If the set-up time is 
2 ns, clock->Q delay is 3 ns and hold time is 1 ns, what is the maximum frequency 
of operation for the circuit?          

 a.  200 MHz b.  333 MHz c.  250 MHz d.  None of the above
 
10.  Which of the following statements is/are true?
I.   Combinational circuits may have feedback, sequential circuits do not.
II.  Combinational circuits have a ‘memory-less’ property, sequential
 circuits do not.
III.  Both combinational and sequential circuits must be controlled by an 
external clock.
a.       I only
b.      II and III only
c.       I and II only
d.      II only
11.              Consider an alternate binary number representation scheme, 
wherein the number of ones M, in a word of N bits, is always the same. This 
scheme is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is 
the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words
 represent able in the latter representation with N bits is 2^N. Hence the
 efficiency is 100%)
a.      Close to 30%
b.      Close to 50%
c.       Close to 70%
d.      Close to 100%
12.   A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority 
of interrupts. Nested interrupts are allowed if later interrupt is higher 
priority than previous one. During a certain period of time, we observe 
the following sequence of entry into and exit from the interrupt service 
routine:
I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end
From this sequence, what can we infer about the interrupt routines?
a.       I3 > I4 > I2 > I1
b.      I4 > I3 > I2 > I1
c.       I2 > I1; I3 > I4 > I1
d.      I2 > I1, I3 > I4 > I2 > I1
13.               I decide to build myself a small electric kettle to boil my 
cup of tea. I need 200 ml of water for my cup of tea. Assuming that typical 
tap water temperature is 25 C and I want the water boiling in exactly one 
minute, then what is the wattage required for the heating element?
[Assume: Boiling point of water is 100 C, 1 Calorie (heat required to change 
1 gm of water by 1 C)= 4 joules, 1 ml of water weighs 1 gm.]
a.       Data given is insufficient
b.      800 W
c.       300 W
d.      1000 W
e.       250 W
14.              The athletics team from REC Trichy is traveling by train. 
The train slows down, (but does not halt) at a small wayside station that has  
a 100 mts long platform. The sprinter (who can run 100 mts in 10 sec) decides 
to jump down and get a newspaper and some idlis. He jumps out just as his compartment enters the platform and spends 5 secs buying his newspaper that 
is at the point where he jumped out. He then sprints along the platform to 
buy idlis that is another 50 mts. He spends another 5 secs  buying the idlis. 
He is now  just 50 mts from the other end of the platform where the train is 
moving out. He begins running in the direction of the train and the only other 
open door in his train is located 50 mts behind the door from where he jumped. 
At what(uniform) speed should the train be traveled if he just misses jumping 
into the open door at the very edge of the platform? Make the following 
assumptions
·         He always runs at his peak speed uniformly
·         The train travels at uniform speed
·         He does not wait (other than for the idlis & newspaper) 
or run baclwards
b.      Data given is insufficient
c.       4 m/s
d.      5 m/s
e.       7.5 m/s
f.       10 m/s
15.              State which of the following gate combinations does not 
form a universal logic set:
a.       2-input AND + 2-input OR
b.      2-to-1 multiplexer
c.       2-input XOR + inverter
d.      3-input NAND
16.              For the circuit shown below, what should the function F be, 
so that it produces an output of the same frequency (function F1), and an 
output of double the frequency (function F2).      
           
a.       F1= NOR gate and F2= OR gate
b.       F1=NAND gate and F2= AND gate
c.       F1=AND gate and F2=XOR gate
d.      None of the above
17.   The FSM (finite state machine) below starts in state Sa, which is the 
reset state, and detects a particular sequence of inputs leading it to state 
Sc. FSMs have a few characteristics. An autonomous FSM has no inputs. For a 
Moore FSM, the output depends on the present state alone. For a Mealy FSM, 
the output depends on the present state as well as the inputs. Which of 
the statements best describes the FSM below?
a.       It has two states and is autonomous
b.       The information available is insufficient
c.       It is a Mealy machine with three states
d.      It is a Moor machine with three states
18.     In the circuit given below, the switch is opened at time t=0. Voltage 
across the capacitor at t=infinity is:
a.       2V
b.      3V
c.       5V
d.      7V
        
19.   What is the functionality represented by the following circuit?
a.       y= ! (b+ac)
b.      y= ! (a+bc)
c.       y= ! (a(b+c))
d.      y= ! (a+b+c)
20.              The value (0xdeadbeef) needs to stored at address 0x400. 
Which of the below ways will the memory look like in a big endian machine:
            0x403  0x402              0x401              0x400
a.         be        ef         de        ad
b.         ef         be        ad        de
c.         fe         eb        da        ed
d.         ed        da        eb        fe
21.               In a given CPU-memory sub-system, all accesses to the 
memory take two cycles. Accesses to memories in two consecutive cycles can
therefore result in incorrect data transfer. Which of the following access
mechanisms guarantees correct data transfer?
a.  A read operation followed by a write operation in the next cycle.
b.  A write operation followed by a read operation in the next cycle.
c.  A NOP between every successive reads & writes
d. None of the above
22.  An architecture saves 4 control registers automatically on function entry 
(and restores them on function return). Save of each registers costs 1 cycle 
(so does restore). How many cycles are spent in these tasks (save and restore) 
while running the following un-optimized code with n=5:
   Void fib(int n)
{
   if((n==0)  (n==1)) return 1;
   return(fib(n-1) + fib(n-2));
}
a.  120
b.  80
c.  125
d.  128
23.  The maximum number of unique Boolean functions F(A,B), realizable for a 
two input (A,B) and single output (Z) circuit is:  
a.       2
b.      6
c.       8

Pattern  Consist of
Technical Test
Contains three sections (Data Structures and Algorithms, Analog Circuits, 
Digital Circuits) you have to choose any two sections among the three. Each 
section has 10 questions each and the total time for the two sections is 
45 minutes. There is negative marking.
Aptitude Test
75 questions – 1 hour – Negative marking is there
Technical Interview
Behavioral Interview
 Here is some sample Questions
int fact(int n) int fact_ii(int n) { { if (n >0)  int fact_val = 1, i = 0; 
return n*fact (n-1); for (i = 1; i <= n ; i++) else fact_val = fact_val*i;
 return 1; return fact_val; } } (a) (i) only(b) (ii) only(c) both(d) None 
of these
(2) Which of the following is a semantic error?(a) Division by zero(b) Missing 
of a semicolon at the end of a statement(c) Assigning a single precision real 
value to a long integer(d) All the above
(3) If the following code segment is to count the no of zero’s in the given
 integer ‘x’ in its binary representation, what is to replaced by CONDITION? 
 int i, count, x;  for(i=0, count=0;i<16;i++)  if(CONDITION) count++; 
a. (x & (1 << i))      b. (x & (1 << i))
c. (x && (1 << i)) d. None of the above.
A graph was given and asked to find out the minimum no of colors required to 
color the graph?                  
(a)  1(b)  2(c)  3(d)  The graph can’t be colored

Inorder traversal of a binary tree is d c e b a and preorder traversal of a
 binary tree is b c d e a. Find out the post order traversal?(6) Which is 
not an advantage of using subroutines?
(a) Easier maintenance(b) Runtime reduces
(c) Storage space reduces(d) Modularity
A k-diagonal matrix is a n *n square matrix in which the elements on the 
principal diagonal and k diagonals above the principal diagonal and k 
diagonals below the principal diagonal only have none zero elements. Other 
elements are zero’s. In order to save the space, the non zero elements are 
stored in a one dimensional array. The no of locations in this array are:
(a) n*(n-k-1)/2             (b) n*(n-1) – (n-k)(n-k-2)
(c) n*(n-1) – (n-k)(n-k-2)  (d) n*n – (n-k-1)
A 1D - array A whose size is N is given and is divided into P partitions 
and an element x is to be searched in the array. Each partition is given 
to one processor. The elements are searched with in the partition using a 
binary search. What is the time complexity of the algorithm? 
(a) O (N/P)(b) O (P)(c) O ( log (N/P))(d) O ( log (N/P)) + O (P log P)
Write the code segment to insert an element p into the linked list after 
an element q? Make necessary pointer adjustments?Ans: p.next = q.next;q.next = p;
 Given a matrix A. What is the minimum no of multiplications do u need to compute
 A10 ?(a) 9(b) 5(c) 4(d) 6



texasinstruments
Sample Questions
1. For a CMOS inverter, the transition slope of Vout vs Vin DC characteristics 
can be increased
          (steeper transition) by: 
a. Increasing W/L of PMOS transistor
b. Increasing W/L of NMOS transistor
c. Increasing W/L of both transistors by the same factor
d. Decreasing W/L of both transistor by the same factor
2.  Minimum number of 2-input NAND gates that will be required to implement 
the function:  Y = AB + CD + EF is
a. 4
b. 5
c. 6
d. 7
3. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed 
first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the 
miss penalty (the time to get the data from M2 in case of a miss) is 100
 nanoseconds. The probability that a valid data is found in M1 is 0.97. 
The average memory access time is:
a. 4.94 nanoseconds
b. 3.06 nanoseconds
c. 5.00 nanoseconds
d. 5.06 nanoseconds
4. Interrupt latency is the time elapsed between:
a. Occurrence of an interrupt and its detection by the CPU
b. Assertion of an interrupt and the start of the associated ISR
c. Assertion of an interrupt and the completion of the associated ISR
d. Start and completion of associated ISR
5.  Which of the following is true for the function (A.B + A’.C + B.C)
a. This function can glitch and can be further reduced
b. This function can neither glitch nor can be further reduced
c. This function can glitch and cannot be further reduced
d. This function cannot glitch but can be further reduced
6. For the two flip-flop configuration below, what is the relationship of 
the output at B to the clock frequency?
a. Output frequency is 1/4th the clock frequency, with 50% duty cycle
b. Output frequency is 1/3rd the clock frequency, with 50% duty cycle
c. Output frequency is 1/4th the clock frequency, with 25% duty cycle
d. Output frequency is equal to the clock frequency
          
7.The voltage on Node B is:
e. 0
f. 10
g. –10
    
8.A CPU supports 250 instructions. Each instruction op-code has these fields:
• The instruction type (one among 250)
• A conditional register specification
• 3 register operands
• Addressing mode specification for both source operands
The CPU has 16 registers and supports 5 addressing modes. What is the 
instruction op-code length in bits?
h. 32
i. 24
j. 30
k. 36
7.  In the iterative network shown, the output Yn of any stage N is 1 
if the total number of 1s at the inputs starting from the first stage 
to the Nth stage is odd. (Each identical box in the iterative network 
has two inputs and two outputs). The optimal logic structure for the 
box consists of:
a. One AND gate and one NOR gate
b. One NOR gate and one NAND gate
c. Two XNOR gates
d. One XOR gate


8. Consider a circuit with N logic nets. If each net can be stuck-at 
either values 0 and 1, in how many ways can the circuit be faulty such 
that only one net in it can be faulty, and such that up-to all nets in 
it can be faulty?
a. 2 and 2N
b. N and 2^N
c. 2N and 3^N-1
d. 2N and 3N
9.  In the circuit shown, all the flip-flops are identical. If the set-up 
time is 2 ns, clock->Q delay is 3 ns and hold time is 1 ns, what is the 
maximum frequency of operation for the circuit?
           

 a.  200 MHz
 b.  333 MHz
 c.  250 MHz
 d.  None of the above
 
10. Which of the following statements is/are true?
I. Combinational circuits may have feedback, sequential circuits do not.
II.Combinational circuits have a ‘memory-less’ property, sequential 
circuits do not.
III.  Both combinational and sequential circuits must be controlled 
by an external clock.
a. I only
b. II and III only
c. I and II only
d. II only
11. Consider an alternate binary number representation scheme, wherein 
the number of ones M, in a word of N bits, is always the same. This scheme
 is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is the 
efficiency of this coding scheme as against the regular binary number 
representation scheme? (As a hint, consider that the number of unique 
words represent able in the latter representation with N bits is 2^N. 
Hence the efficiency is 100%)
a. Close to 30%
b. Close to 50%
c. Close to 70%
d. Close to 100%
12. A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority 
of interrupts. Nested interrupts are allowed if later interrupt is higher 
priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:

I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end
From this sequence, what can we infer about the interrupt routines?
a. I3 > I4 > I2 > I1
b. I4 > I3 > I2 > I1
c. I2 > I1; I3 > I4 > I1
d. I2 > I1, I3 > I4 > I2 > I1
13.  I decide to build myself a small electric kettle to boil my cup of tea. 
I need 200 ml of water for my cup of tea. Assuming that typical tap water temperature is 25 C and I want the water boiling in exactly one minute, then
 what is the wattage required for the heating element?
[Assume: Boiling point of water is 100 C, 1 Calorie 
(heat required to change 1 gm of water by 1 C)= 4 joules, 
1 ml of water weighs 1 gm.]
a. Data given is insufficient
b. 800 W
c. 300 W
d. 1000 W
e. 250 W
14. The athletics team from REC Trichy is traveling by train. The train 
slows down, (but does not halt) at a small wayside station that has  a 
100 mts long platform. The sprinter (who can run 100 mts in 10 sec) decides 
to jump down and get a newspaper and some idlis. He jumps out just as his 
compartment enters the platform and spends 5 secs buying his newspaper that 
is at the point where he jumped out. He then sprints along the platform to buy
 idlis that is another 50 mts. He spends another 5 secs  buying the idlis. 
He is now  just 50 mts from the other end of the platform where the train is 
moving out. He begins running in the direction of the train and the only other 
open door in his train is located 50 mts behind the door from where he jumped. 
At what(uniform) speed should the train be traveled if he just misses jumping 
into the open door at the very edge of the platform? Make the following
assumptions
• He always runs at his peak speed uniformly
• The train travels at uniform speed
• He does not wait (other than for the idlis & newspaper) or run 
baclwards
b. Data given is insufficient
c. 4 m/s
d. 5 m/s
e. 7.5 m/s
f. 10 m/s
15. State which of the following gate combinations does not form a universal 
logic set:
a. 2-input AND + 2-input OR
b. 2-to-1 multiplexer
c. 2-input XOR + inverter
d. 3-input NAND
16. For the circuit shown below, what should the function F be, so that it
 produces an output of the same frequency (function F1), and an output of 
double the frequency (function F2).  




 
a. F1= NOR gate and F2= OR gate
b. F1=NAND gate and F2= AND gate
c. F1=AND gate and F2=XOR gate
d. None of the above
17. The FSM (finite state machine) below starts in state Sa, which is the 
reset state, and detects a particular sequence of inputs leading it to state 
Sc. FSMs have a few characteristics. An autonomous FSM has no inputs. For a 
Moore FSM, the output depends on the present state alone. For a Mealy FSM, 
the output depends on the present state as well as the inputs. Which of 
the statements best describes the FSM below?
a. It has two states and is autonomous
b. The information available is insufficient
c. It is a Mealy machine with three states
d. It is a Moor machine with three states


18. In the circuit given below, the switch is opened at time t=0. Voltage 
across the capacitor at t=infinity is:
a. 2V
b. 3V
c. 5V
d. 7V
     
   
19. What is the functionality represented by the following circuit?
a. y= ! (b+ac)
b. y= ! (a+bc)
c. y= ! (a(b+c))
d. y= ! (a+b+c)

20. The value (0xdeadbeef) needs to stored at address 0x400. Which of 
the below ways will the memory look like in a big endian machine:
 0x403 0x402  0x401  0x400
a.  be ef de ad
b. ef be ad de
c. fe eb da ed
d. ed da eb fe
21.  In a given CPU-memory sub-system, all accesses to the memory take 
two cycles. Accesses to memories in two consecutive cycles can therefore 
result in incorrect data transfer. Which of the following access mechanisms
guarantees correct data transfer?
a. A read operation followed by a write operation in the next cycle.
b. A write operation followed by a read operation in the next cycle.
c. A NOP between every successive reads & writes
d. None of the above
22. An architecture saves 4 control registers automatically on function 
entry (and restores them on function return). Save of each registers costs 
1 cycle (so does restore). How many cycles are spent in these tasks 
(save and restore) while running the following un-optimized code with 
n=5:
   Void fib(int n)
{
 if((n==0)  (n==1)) return 1;
 return(fib(n-1) + fib(n-2));
}
a. 120
b. 80
c. 125
d. 128
23. The maximum number of unique Boolean functions F(A,B), realizable for a 
two input (A,B) and single output (Z) circuit is:  
a. 2
b. 6
c. 8

Pattern  Consist of
Technical Test
Contains three sections (Data Structures and Algorithms, Analog Circuits, 
Digital Circuits) you have to choose any two sections among the three. Each 
section has 10 questions each and the total time for the two sections is 
45 minutes. There is negative marking.
Aptitude Test
75 questions – 1 hour – Negative marking is there
Technical Interview
Behavioral Interview
 Here is some sample Questions
1. int fact(int n) int fact_ii(int n)
{ {
if (n >0)
  int fact_val = 1, i = 0;
return n*fact (n-1); for (i = 1; i <= n ; i++)  else fact_val = fact_val*i;  
return 1; return fact_val;  } }  
(a) (i) only (b) (ii) only (c) both (d) None of these 
2. (2) Which of the following is a semantic error? 
(a) Division by zero (b) Missing of a semicolon at the end of a statement 
(c) Assigning a single precision real value to a long integer 
(d) All the above 3. 
(3) If the following code segment is to count the no of zero’s in the given
 integer ‘x’ in its binary representation, what is to replaced by CONDITION?
 int i, count, x;   for(i=0, count=0;i<16;i++) next =" q.next;" next =" p;">